1. Field of the Invention
This invention is related to an electronically reprogrammable nonvolatile semiconductor memory device. Within nonvolatile semiconductor memory devices, it is related to a nonvolatile semiconductor memory device such as an EEPROM etc. of the NAND cell type, the NOR cell type, the DINOR cell type, or the AND cell type.
2. Description of the Related Art
Conventionally, an electronically reprogrammable EEPROM is known as one type of semiconductor memory device. Within these, a NAND cell type EEPROM (NAND type flash memory), which is composed of a NAND cell block connecting a plurality of memory cells in series, is receiving attention for being highly integrated compared to other memories. The conventionally used data program and erasure operations of the in a NAND cell type EEPROM are as follows.
The data program operation is mainly performed in sequence from the memory cell which is located the furthest away from the bit line. First, when the data program operation begins, 0V (“0” data program) or a power supply voltage Vcc (“1” data program) is applied to the bit line and Vcc is applied to the selected gate line of the side of the selected bit line.
In this case, when the bit line is at 0V, in the connected selected NAND cell, the channel section within the NAND cell through a selected gate transistor is at 0V. When the bit line is at Vcc, in the connected selected NAND cell, after the channel section within the NAND cell is charged through a selected gate transistor up to (Vcc−Vtsg) (where Vtsg is the select gate transistor's threshold voltage) the channel section takes on a floating state.
Subsequently, the control gate line of the selected memory cell within the selected NAND cell is applied with 0V to Vpp (Vpp is about 20V: a program high level voltage) and the control gates of the non-selected memory cells within the selected NAND cell are applied with 0V to Vmg (Vmg is about 10V: a medium level voltage).
Here, when the bit line is at 0V, because the channel section within the NAND cell in the connected selected cell is at 0V, a large voltage potential difference occurs between the selected memory cell gate within the selected NAND cell (=Vpp voltage) and the channel section (=0V) and electrons are injected from the channel section into the floating gate. By this, the threshold voltage of that selected memory cell is shifted in a positive direction. This state is “0.”
Alternatively, when the bit line is at Vcc, because the channel section within the NAND cell in the connected selected NAND cell is in a floating state, following the voltage increase (0V→Vpp, Vmg) in the control gate under the influence of capacity coupling between the control gate line within the selected NAND cell and the channel section, the voltage of the channel section, while maintaining a floating state, increases from (Vcc−Vtsg) volts to Vmch (=about 8V). At this time, because the voltage potential difference between the selected memory cell gate (=Vpp volts) and the channel section (=Vmch) is relatively small at about 12V, electron injection does not occur and therefore the voltage threshold of the selected memory cell does not change and the negative threshold is maintained. This state is “1.”
Data erasure in the NAND cell type EEPROM is done upon all the memory cells within the selected NAND cell block simultaneously. More specifically, all the control gates within the selected NAND cell block are applied with 0V, the bit lines, the source line, the control gates within the non-selected NAND cell block and all the selected gates are is made to float and the p type well (or p type plate) is applied with a high level voltage of about 20V. By this, the electrons in the floating gates are released into the p type well (or the p type plate) in all the memory cells within the selected NAND cell block and the voltage threshold is shifted in a positive direction. In this way, in the NAND cell type EEPROM, data erasure is done at once in block units.
At the time of a data read operation, the control gate of the selected memory cell is applied with 0V and the control gates and select gates of all the other memory cells are applied with a voltage (for example 5V), which is regulated from the stress caused at the time of the read-out operation, and a data read is carried out by detecting whether an electric current within the selected memory cell occurs.
From the constraint of read operations, as stated above, when 5V, for example, is the voltage regulated from the stress at the time of a read operation, the voltage threshold after “0” data program must be controlled between 0V and about 4V. Because of this, program verify operations take place, and only the memory cells which are deficient in “0” program are detected and reprogram data is set so that a reprogram can be performed only on the memory cells deficient in “0” program (each-bit-verify). A memory cell deficient in “0” program is detected by read-out operation (verify read-out) with the selected control gate being applied with, for example, 0.5V (a voltage for verifying). In other words, if the memory cell voltage threshold is not more than 0.5V, which is a margin enough toward 0V, there occurs an electric current in the selected memory and a deficiency in “0” program is detected.
By programming data with repeated program operations and program verify operations, the program time is optimized and “0” program voltage threshold is controlled between 0V and about 4V in the individual memory cells.
In this kind of a NAND cell type EEPROM, because the program voltage at the time of program is maintained at Vpp, in the early program stage, in which the charge storage layer holds a relatively small amount of electrons, the change in the memory cell voltage threshold is fast, and in the later program stage, in which the charge storage layer holds a relatively large amount of electrons after electrons are injected into the charge storage layer, the change in the memory cell voltage threshold is slow. Also, in the early program stage, the electrical field, which is applied to the insulation layer in which tunnel current flows, is strong but in later program stages the electrical field becomes weak.
As a result of this, when program voltage Vpp is increased in order to increase the speed of programming, the largest voltage threshold after programming becomes so high and the distribution of the values of thresholds after programming becomes so wide that the electrical field which is applied to the insulation layer, in which tunnel current flows, also becomes stronger and reliability also becomes worse. Conversely, when Vpp is lowered in order to narrow the distribution of the values of threshold after programming, the speed of programming becomes slower. In other words, there is a problem whereby the program voltage margin is narrow. Also, there is the problem that as a data program operation or a erasure operation progresses the efficiency of the data program operation or the erasure operation worsen.
Considering the above stated problems, the Japan patent application KOKAI publication No. H07-169284 and the non-patent document by G. J. Hemink et al. in the Symposium on VLSI Technology Digest of Technical Papers, 1995, pp. 129-130 propose methods which gradually increase the program voltage Vpp while repeating cycles of the program operations and each bit verify operations. In the method cited in the Japan patent application KOKAI publication No. H07-169284, only the Vpp is constantly increased each cycle by ΔVpp, and the program time Δt is maintained constant. Also, ΔVpp and Δt are set so that the distribution of the values of thresholds after “0” programming becomes ΔVpp.
It is the purpose of this invention to provide a nonvolatile semiconductor memory device and an operation method thereof which can prevent a reduction of efficiencies of a data program operation and an erasure operation and is able to shorten the time necessary for a data program operation and a data erasure operation.